Research interests

I work in the design of mixed signal integrated circuits and their test. Specifically, I have worked on

  • Repeaterless low swing on-chip interconnects
    • Equalizers
    • Clock retiming circuits
  • Testability of mixed signal circuits
  • Modeling and analysis of settling time of clock retiming circuits
  • Instrumentation circuits for Piezo-resistive sensors
  • Interface circuits for MEMS based sensors
Ongoing Collaborations
  • Seena V, Associate Prof. at Indian Institute of Space Science and Technology, for work related to design of MEMS sensors and read out circuits and instrumentation circuits for MEMS sensors.

You can read about my publications here. Also take a look at the Chips galley to see some of the experimental setups and chips I have designed.

Ph.D. Research: Repeaterless Low-Swing On-Chip Interconnects

Abstract: CMOS technology, with its continuous technology scaling, has been able to improve the performance of digital processing systems in every new generation. Performance of transistors improves as technology scales and this, coupled with smaller device dimensions and larger die dimensions, allows very sophisticated systems to be built. However, the performance of interconnects has not been scaling equally well. Long interconnects in particular have now become the performance bottlenecks in these systems. Repeater insertion is widely used to alleviate this problem, but it comes with high power consumption, routing complexity and increase in the active area of interconnects.

These limitations have stimulated extensive research in low swing repeaterless interconnects that use equalizers to achieve high performance with low power. The promise shown by these schemes has raised a lot of interest. However, it has also led to reservations about their adoption in mainstream digital system design because these interconnects use mixed signal and low swing circuits. The high latency of interconnects necessitates clock synchronization. Since the latency of long interconnects is high, and can vary with environmental changes, measuring this latency and its variation with time accurately is important for understanding and designing systems. The testability of these interconnect schemes in the established digital design flow has also raised concerns.

In this thesis, we have tried to address these concerns. The thesis reports circuits for performing equalization at the transmitter and receiver. Design optimization methods are presented, which allow fast and efficient design of these interconnects. We then report a clock synchronizing circuit suitable for repeaterless low swing interconnects. The synchronizer includes a clock domain transfer to the receiver clock domain. This effectively makes the interconnect a transparent digital interconnect. We then demonstrate that with the addition of a little circuitry, these mixed signal systems can be tested along with the rest of the digital system using established digital test methods.

Finally, we study the settling time of mesochronous clock retiming circuits in the presence of timing jitter. We show how timing jitter can result in large, and possibly indefinite, increase in the settling time. By modeling the system as a Markov chain, we analyze the effects of different types of jitter, which include data dependent jitter, random jitter and also simultaneous data dependent and random jitter. Using the insights provided by the model, different synchronizers with reduced settling time are then proposed and verified with circuit simulations.